CPU for UPSC ISS is the first thing the syllabus names after “operations of a computer”, and it is the one hardware topic where candidates stop at the surface. Everyone knows the CPU has an ALU and a control unit. Very few know which register holds the next instruction, and that is the question the paper actually asks.
Quick answer. The CPU has produced 12 questions in the last ten papers, an average of 1.2 a year, or 3 marks. The questions split into four clusters: the units inside the CPU, the named registers, the machine cycle, and RISC against CISC. None of them is difficult. All of them are specific.
Statistics Paper I, Section IV. Syllabus items: operations of a computer, and different units of a computer system like central processing unit, arithmetic and logical unit. With memory and peripherals, this module is worth 47 questions and about 11.75 marks a year.
The five operations of a computer
The syllabus opens with “operations of a computer”, and every machine performs the same five, whatever its size.
| Operation | What happens |
|---|---|
| Input | Accepting data and instructions from the user |
| Storage | Holding data and instructions so they can be reached |
| Processing | Turning raw data into meaningful information |
| Output | Presenting the result in human readable form |
| Control | Coordinating every other unit inside the system |
Processing is done by the CPU and the memory unit together. The monitor plays no part in processing. That distinction has been asked directly, with the monitor sitting in the options waiting for a careless answer.
The stored program concept
John von Neumann’s contribution in the late 1940s is the foundation of every modern computer. Both the data and the instructions are read into the same memory before processing begins, and both travel to the processor over a shared bus.
That shared path is the whole idea. It is also why the architecture carries a known bottleneck, because instructions and data cannot move at the same instant.
Inside the CPU
The CPU is not one block. It has three parts, and the paper tests how they relate to each other.
The Arithmetic and Logic Unit
The ALU does the actual work. It has two halves.
| Half | Handles |
|---|---|
| Arithmetic unit | Addition, subtraction, multiplication, division |
| Logic unit | Comparisons and boolean operations: AND, OR, NOT |
A question has asked which unit handles AND and OR. The answer is the logic unit, not the arithmetic unit and not the ALU as a whole, because both appear as separate options. Read the options before answering.
The Control Unit
The control unit does no processing at all. It fetches instructions, decodes them, and directs the ALU, memory and peripherals on what to do next. It is the manager, not the worker.
The relationship trap. The ALU is a component of the CPU, not of the control unit. The control unit is also a component of the CPU. Neither contains the other, and the CPU is certainly not a component of the control unit. A 2018 question built three statements on exactly this confusion.
Registers
Registers are tiny storage locations built inside the CPU. They are the fastest memory in the entire machine and the smallest. This is where most candidates stop reading, and it is where the marks are.
| Register | Full name | Holds |
|---|---|---|
| PC | Program Counter | The address of the next instruction to be executed |
| IR | Instruction Register | The instruction currently being executed |
| MAR | Memory Address Register | The address of the memory location being read or written |
| MBR or MDR | Memory Buffer or Data Register | The data travelling to or from that location |
| Accumulator | Accumulator | The result produced by the ALU |
Four of these five have been asked by name. Program counter in 2022, memory address register in 2017, accumulator in 2026. Learn the table, not the concept.
MAR against MBR in one line. MAR holds where, MBR holds what. If you can separate those two, you have both marks.
Worked Example 1: One instruction through the machine cycle
Every instruction goes through four phases. Watching the registers move makes the whole thing concrete.
Instruction: add the number stored at address 2050 to the accumulator.
| Phase | What happens | Registers involved |
|---|---|---|
| 1. Fetch | The control unit reads the next instruction from memory | PC gives the address to MAR, the instruction arrives in IR, PC moves on |
| 2. Decode | The control unit works out what the instruction means | IR is read and interpreted |
| 3. Execute | The ALU performs the addition | MAR holds 2050, MBR brings the value, the ALU adds |
| 4. Store | The result is written back | The accumulator holds the result |
The four phases are fetch, decode, execute, store. In that order, every time.
Worked Example 2: How many machine cycles
This one has been asked as a statement inside a longer question.
A program consists of 6 machine language instructions. How many machine cycles are needed?
One machine cycle handles exactly one machine language instruction. Six instructions therefore need six machine cycles.
There is nothing clever here. The question tests whether you know the cycle is per instruction and not per program.
Worked Example 3: Reading processor speed
Processor speed is measured in hertz, which counts clock cycles per second.
| Unit | Cycles per second |
|---|---|
| 1 MHz | 1 million |
| 1 GHz | 1 billion |
| 3 GHz | 3 billion |
A 3 GHz processor runs 3 billion clock cycles every second. A machine cycle usually needs several clock cycles, so this is not the same as three billion instructions.
Do not confuse the units. Processor speed is GHz. Scanner and printer resolution is dpi. Memory size is bytes. A 2016 question put all three in one statement set.
The system bus
A bus is the set of wires that carries information between components. Three of them run together, and the paper has asked which does what.
| Bus | Carries | Direction |
|---|---|---|
| Data bus | The actual data and instructions | Both ways |
| Address bus | The memory address being accessed | One way, from the CPU |
| Control bus | Timing and command signals | Both ways |
The three together are called the system bus, and that is the answer to a question asking which bus manages the transfer of data and addresses among the various components.
Address bus width decides how much memory you can reach. An n line address bus can address 2ⁿ locations. That formula returns in the memory article, where it is asked as a calculation.
RISC and CISC
Two philosophies of processor design. Three questions in four years, and the old series did not cover it.
| CISC | RISC | |
|---|---|---|
| Full form | Complex Instruction Set Computer | Reduced Instruction Set Computer |
| Instruction set | Large, many complex instructions | Small, simple instructions only |
| Instruction length | Variable | Fixed, typically 32 bits |
| Clock cycles per instruction | Several | Usually one |
| Instruction complexity | Work done in hardware | Work done in software by combining instructions |
| Chip size and power | Larger, more power | Compact, less power |
| Typical use | Desktop processors | Mobile and embedded processors |
Why RISC is often preferred: a compact chip and a small instruction set. Note carefully that executing multiple clock cycles is a CISC trait, not a RISC advantage. That exact wrong option has appeared in the paper.
RISC instruction format is fixed length, and the standard figure asked is 32 bits.
How This Gets Asked
The relationship question [2018]
Consider the following statements: 1. ALU is a component of Control Unit. 2. CPU is a component of Control Unit. 3. Control Unit is not a component of CPU.
All three are wrong. The CPU contains the ALU and the control unit. Nothing here contains the CPU.
This is the most common shape of question in the whole Computer section. Three statements, all built on one relationship, and the paper is checking whether you know which box sits inside which.
The register question, three times [2017, 2022, 2026]
What is the purpose of the Memory Address Register? [2017]
Which one of the following registers keeps track of the next instruction to be executed? [2022]
Which one of the following is used for storing the results produced by the arithmetic and logic unit? [2026]
MAR, then program counter, then accumulator. Three different registers, three different papers, one table.
If you learned only “the CPU has registers”, you lost all three marks. If you learned the five row table above, you have all three.
The RISC question, twice [2023 and 2026]
RISC processors are always preferred to CISC processors because of: 1. Compact size 2. Small instruction set 3. Executing multiple clock cycles [2023]
What is the fixed length of the instruction format used in RISC processors? [2026]
The first tests the trap, which is that multiple clock cycles is a CISC characteristic. The second tests a single number, 32 bits.
Quick Revision Table
| Point | Value |
|---|---|
| Five operations | Input, storage, processing, output, control |
| Processing is done by | CPU and memory unit, not the monitor |
| Stored program concept | Von Neumann, data and instructions in the same memory |
| CPU contains | ALU, control unit, registers |
| ALU contains | Arithmetic unit and logic unit |
| AND, OR, NOT are handled by | The logic unit |
| Control unit does | Fetch, decode and direct. No processing |
| Program counter holds | Address of the next instruction |
| Instruction register holds | The current instruction |
| Memory address register holds | The address being accessed |
| Memory buffer register holds | The data being transferred |
| Accumulator holds | The result from the ALU |
| Machine cycle phases | Fetch, decode, execute, store |
| Machine cycles for 6 instructions | 6 |
| Processor speed unit | GHz |
| Buses | Data, address, control, together the system bus |
| n address lines can reach | 2ⁿ locations |
| RISC instruction length | Fixed, 32 bits |
| CISC instruction length | Variable |
| Multiple clock cycles per instruction | A CISC trait, not a RISC advantage |
Practice Set
Ten questions. No answer key below.
Write your answers in the comments, all ten in a single comment, in the format 1-b 2-a 3-d and so on. The full answer key is posted in this same thread after seven days.
A year in brackets means the question is from that paper. The rest are written in the same pattern.
- What is the purpose of the Memory Address Register? [2017]
- A bus that manages the transfer of data and addresses among various components is [2019]
- By using which of the following units is data processing performed by a computer system? 1. Monitor 2. Memory unit 3. CPU [2022]
- Consider the following statements in respect of machine cycle: 1. It consists of four phases, namely fetching, decoding, executing and storing. 2. It is a cycle in which machine language instructions are executed. 3. If a program consists of 6 machine language instructions, 6 separate machine cycles would be executed to run the program. Which of the statements given above are correct? [2022]
- RISC processors are always preferred to CISC processors because of: 1. Compact size 2. Small instruction set 3. Executing multiple clock cycles [2023]
- Which of the following are main operations of CPU? I. Fetching instructions from the memory II. Decoding the instructions III. Executing the instructions IV. Storing the results back in the memory [2024]
- AND and OR operations are part of which unit of CPU? [2025]
- What is the fixed length of the instruction format used in RISC processors? [2026]
- Which one of the following is used for storing the results produced by the arithmetic and logic unit? [2026]
- Consider the following statements: I. The address bus carries data in both directions between the CPU and memory. II. An address bus of n lines can address 2ⁿ distinct memory locations. Which of the statements given above is or are correct?
Frequently Asked Questions
How many questions come from the CPU in UPSC ISS?
Twelve across the ten papers from 2017 to 2026, about 1.2 a year, worth 3 marks. Combined with memory and peripherals, the hardware module is worth 47 questions.
Is the ALU a part of the control unit?
No. Both the ALU and the control unit are components of the CPU. Neither is inside the other, and questions built on this confusion appear regularly.
Which register keeps track of the next instruction?
The program counter. The instruction register holds the instruction currently being executed, which is the option most often confused with it.
What is the difference between MAR and MBR?
The memory address register holds the address of the location being accessed. The memory buffer register holds the data moving to or from that location. MAR holds where, MBR holds what.
What are the four phases of the machine cycle?
Fetch, decode, execute and store, in that order. One machine cycle handles one machine language instruction, so a six instruction program needs six cycles.
Is RISC better than CISC?
RISC offers a compact chip, a small fixed length instruction set and lower power use, which is why mobile devices use it. Executing multiple clock cycles per instruction is a CISC characteristic and has appeared as a wrong option.
Do I need to know processor architecture in depth for UPSC ISS?
No. The syllabus names the units of a computer system, and the questions stay at the level of what each unit does and which register holds what. Pipelines, caches inside the CPU and micro architecture have never been asked.
Related Reading
- Computer Application for UPSC ISS: Complete 16 Part Series
- Computer Memory for UPSC ISS
- Input and Output Devices for UPSC ISS
- Number Systems for UPSC ISS
Part 3 of 16 in the Computer Series for UPSC ISS. Previous: Binary Codes for UPSC ISS. Next: Computer Memory for UPSC ISS, published 7 October at 8:00 AM.
